1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a trench capacity type memory cell of a dynamic random access memory (DRAM) device.
2. Description of the Related Art
A memory cell of a DRAM device is constructed by a single transfer gate transistor and a single capacitor to make the device simple. Such a structure is widely used as it is suitable for highly integrated DRAMs. Three-dimensionally configured capacitors have been developed and used for such memory cells to realize a higher degree of integration for DRAM devices.
The three-dimensionally configured capacitors of the memory cell of a DRAM device may be either of a stacked structure or of a trenched structure. While these structures have respective advantages and disadvantages, the trenched structure is advantageous from the viewpoint of realizing an excellent flatness for the surface of the device and hence can effectively be used for a system-on-silicon type semiconductor device including both logic circuits and memory circuits.
Various possible structural alternatives have been studied for capacitors of the trenched structure. One of such alternatives is realized by forming a cell plate electrode on the silicon substrate side for the capacitor and a capacitor electrode in the inside of a trench to provide strong resistance against noises caused by incident .alpha.-rays and/or coming from the circuit. This capacitor will be referred to as a substrate plate type trench capacitor.
In a memory cell formed by a single substrate plate type trench capacitor and a single transfer gate transistor, the impurity diffusion source/drain region of the transfer gate transistor and the capacitor electrode are required to be electrically connected with each other. Various techniques have been proposed to realize the electrical connection.
In a first prior art substrate-plate trench capacitor type memory cell (see JP-A-1-173714), a selective monocrystalline silicon layer is epitaxially grown to bridge over the source/drain region and the capacitor electrode. As a result, the selective silicon layer electrically connects the source/drain region and the capacitor electrode. This will be explained later in detail.
In the above-described first prior art memory cell, a capacitor insulating layer is so thin as to increase the capacitance of the substrate plate type trench capacitor. As a result, the selective silicon layer can bridge over the source/drain region and the capacitor electrode. Thus, under certain conditions, a parasitic MOS transistor can appear in the device. As a result, a leakage current may flow through the parasitic MOS transistor. If the capacitor insulating layer is thickened, such a parasitic MOS transistor can be prevented from becoming operational in the device. In this case, however, it will be difficult to grow the selective silicon layer and realize a reliable electric connection between the source/drain region and the capacitor electrode.
In a second prior art substrate-plate trench-capacitor type memory cell (see-JP-8-88331), a thick insulating layer is formed on the lateral walls in an upper portion of a trench, while a capacitor insulating layer is formed on the lateral walls of the trench in a lower portion of the trench. Also, an anti-inversion layer (channel stopper) is formed on the outer periphery of the trench, and a source/drain region and the capacitor electrode are electrically connected by a connection electrode which is arranged on the top of the thick insulating layer. This also will be explained later in detail.
In the above-described second prior art memory cell, the pattern of the connection electrode is formed by means of a photolithography and etching process. However, as the memory cell is down-sized, the distance between the source/drain region and the capacitor electrode is reduced, which makes it difficult to form a pattern for the connection electrode. Thus, it is difficult to down-size the memory cell so long as the connection electrode is used.